Advances in packaging and integrated circuit assembly processes are increasing the use of integrated circuits or multiple integrated circuits mounted on interposers, wafers or substrates to form modules that are then subsequently mounted to printed circuit boards (“PCBs”) to form complete systems. For example, an integrated circuit may be mounted as a “flip chip” on a substrate that carries solder connectors such as solder balls in a grid array to form a “flip chip ball grid array” (“FC-BGA”) assembly; this assembly may then be mounted to a system board. As the use of increasingly advanced integrated circuits continues and the circuits are used in ever smaller and denser devices, such as portable and battery powered devices, the need for smaller, thinner, and less costly techniques to couple integrated circuit devices and assembled circuit modules to PCBs also continues to increase.
In addition, the use of stacked arrangements such as stacked dies and package-on-package (“PoP”) arrangements are increasingly used. Memory modules and integrated circuits may be vertically arranged in this three dimensional (“3D”) structure. Stacking integrated circuit devices or packaged devices reduces the area needed on the system board, and increases the circuit density to provide system assemblies for mounting to a system board. For example, a memory IC or a complete memory module may be assembled together in a PoP structure with another integrated circuit such as a logic IC, processor, or application processor unit (“APU”), which might be a user defined application specific integrated circuit (“ASIC”). The assembly, which may be referred to as a “package on package” or “PoP” structure, may then be disposed on a substrate or interposer using additional solder connections, for final mounting to a system board using external solder connections, for example, using controlled collapse chip connectors (“C4”) or solder balls. In a typical arrangement, an integrated circuit die may be mounted on the top surface of an interposer formed of a laminate material, silicon, ceramic, films and the like. A solder connection is made between the integrated circuit die and the interposer, using solder bumps, for example. The lower surface of the interposer may also have solder connectors, typically solder balls, arranged in a pattern that corresponds to a ball land or pad pattern on the system board. After the PoP assembly is mounted on the interposer, the completed interposer and PoP assembly may then be mounted on the system PCB using the solder balls, and thermal reflow to bond the PoP assembly to the system board.
The assemblies may have solder connections such as solder bumps, pillars or columns disposed on one surface. Through vias may be formed extending through the PoP assembly and coupled to the redistribution layers (“RDL”) or the solder connections. The RDL layers of the APU are conventionally coupled to the solder connectors using conductive pads formed over an uppermost passivation layer. The solder connections are then referred to as “solder on pads” or “SOP” technology. Forming these solder pads requires photolithographic processes, a specific photo mask for photoresist exposure, and additional metallization and metal patterning steps, which increases costs and lowers throughput by adding manufacturing steps.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale.